1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a destructive readout semiconductor memory device such as a dynamic random access memory or a ferroelectric memory which needs to write back data after the data is read.
2. Description of the Related Art
Included among known semiconductor memories are destructive readout semiconductor memories such as dynamic random access memories (DRAMs) and ferroelectric memories which lose data of a memory cell once the data is readout of the memory cell. Semiconductor memories of this type need a writeback (refresh) operation executed at the same time as data readout, in the case where data is to be retained after readout.
A readout operation of these destructive readout semiconductor memories is described taking a DRAM as an example.
FIG. 10 is a block diagram of a common DRAM. In FIG. 10, a hundred and twenty-eight memory cells 1-1 are connected to one word line 3, and a sense amplifier 26 is connected to the tip of each bit line 21. The sense amplifier 26 is enabled with an enable signal SE. With a bit line selecting signal YSW, a specific bit line is selected, and data read out of a cell and amplified by the bit line's sense amplifier 26 is propagated to a local I/O bus 15 to be input to a data amplifier (DAMP) 9.
Readout of memory cell data is executed by the sense amplifiers 26 illustrated in FIG. 11. Each sense amplifier 26 has two bit lines connected thereto. Data read out of a memory cell is input via one of the two bit lines whereas a voltage that serves as a reference voltage is input to the other bit line. The sense amplifier 26 amplifies an electric potential difference between the voltage read out of the memory cell and the reference voltage, to thereby establish whether the data logic is “H” or “L.”
FIG. 12 illustrates an operation timing chart. After a word line is selected, the sense amplifier enable signal SE rises to enable the sense amplifier 26, which proceeds to amplify data. A bit line is then selected with the bit line selecting signal YSW, and the data is read to the outside. Reading the data to the bit line 21 causes the memory cell 1-1 to lose accumulated electric charges, but the data is amplified by the sense amplifier 26 which has been enabled with the sense amplifier enable signal SE, and the data amplified by the sense amplifier 26 is written back via the bit line 21 to the original memory cell from which the data has been read. The memory cell can thus keep the same data after readout. Current consumption peaks after the sense amplifier is enabled.
Aside from destructive readout semiconductor memories which have been described above, some semiconductor memories need to read a plurality of bits concurrently. In such semiconductor memories, a number of sense amplifiers that is determined by the number of bits required to be read concurrently operate at the same time. One bit line is connected to one sense amplifier and, consequently, putting a large number of sense amplifiers in operation at once means that as many bit lines as the operating sense amplifiers are charged concurrently. This increases current consumption instantly, and causes a voltage drop and power supply noise.
JP 2003-272390 A (Patent Document 1) avoids this instant increase in current consumption due to simultaneous operation of sense amplifiers by dividing cells of a memory where data is read in pages into a plurality of groups to constitute a plurality of sense amplifier groups, and then staggering the operation start time of these sense amplifier groups instead of allowing the sense amplifier groups to start operating simultaneously. The peak current registered at the time the sense amplifiers start operating is thus lowered.
JP 2007-157283 A (Patent Document 2) discloses a semiconductor memory device with a synchronous readout function in which sense amplifiers are divided into a plurality of groups and each group staggers the operation timing of its sense amplifiers by timing the sense amplifiers' operation with clock signals. The peak current registered at the time the sense amplifiers are put into operation is thus lowered.
As mentioned above, destructive readout semiconductor memories need writeback executed at the same time as readout. Even if a destructive readout semiconductor memory device executes readout with sense amplifiers divided into groups as in Patent Documents 1 and 2 described above, an operating current for data readout and a bit line charging current for writeback are generated concurrently as soon as the sense amplifiers in the groups start operating. The peak current is therefore not lowered enough.